Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs-Reference-Cited by-同舟云学术

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Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

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Container-title:Proceedings 21st International Conference on Computer Design
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Author:

Dall'Osso M.,Biccari G.,Giovannini L.,Bertozzi D.,Benini L.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/8790/27821/01240952.pdf?arnumber=1240952

Cited by 53 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reducing the number of passing links in the 2D-NoC for performance and reliability improvement;World Journal of Engineering;2020-08-07

2. Performance Comparison of Asynchronous NoC Router Architectures;International Conference on Computer Networks and Communication Technologies;2018-09-18

3. From Latency-Insensitive Design to Communication-Based System-Level Design;Proceedings of the IEEE;2015-11

4. Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat;Circuits, Systems, and Signal Processing;2015-02-21

5. Fixed latency on-chip interconnect for hardware spiking neural network architectures;Parallel Computing;2013-09

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