DC and Analog/RF Performance Analysis of Gate-Drain Underlapped and Channel Engineered TFET-Reference-Cited by-同舟云学术

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DC and Analog/RF Performance Analysis of Gate-Drain Underlapped and Channel Engineered TFET

Published:2022-02-26 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE VLSI Device Circuit and System (VLSI DCS)
language:
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Author:

Ghosh Sudipta¹,Bose Sayan²,Anwar Wahid²,Banerjee Madhusree³,Venkateswaran P.¹,Sarkar Subir Kumar¹

Affiliation:

1. Jadavpur University,Department of Electronices & Telecommunication Engineering,Kolkata,India

2. Meghnad Saha Institute of Technology,Dept. of ECE,Kolkata,India

3. Cognizant Technology Solutions India Private Limited,Quality Engineering & Assurance,Kolkata,India

Funder

Jadavpur University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9811418/9811430/09811483.pdf?arnumber=9811483

Reference18 articles.

1. Dual delta tunnel FET: An energy efficient switch with improved current switching ratio and steeper subthreshold slope

2. Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

3. Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

4. Ambipolar Performance Improvement of Dual Material TFET Using Drain Underlap Engineering

5. Improvement in Reliability of Tunneling Field-Effect Transistor With p-n-i-n Structure

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