DC and Analog/RF Performance Comparison of Renovated GAA JLFET Structures
Author:
Affiliation:
1. Jadavpur University,Dept of E.T.C.E,Kolkata,India
2. Meghnad Saha Institute of Technology,Dept. of ECE,Kolkata,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9811418/9811430/09811488.pdf?arnumber=9811488
Reference18 articles.
1. Performance Analysis of Junctionless Transistors Based on Monte Carlo Simulation
2. Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET
3. Numerical assessment of high-k spacer on symmetric S/D underlap GAA junctionless accumulation mode silicon nanowire MOSFET for RFIC design
4. A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications
5. Analysis and simulation of a junctionless double gate MOSFET for high-speed applications
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1. Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems;Microelectronics Journal;2023-06
2. RF with linearity and non-linearity parameter analysis of gate all around negative capacitance junction less FET (GAA-NC-JLFET) for different ferroelectric thickness;Physica Scripta;2022-09-21
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