HyperLogLog Sketch Acceleration on FPGA-Reference-Cited by-同舟云学术

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HyperLogLog Sketch Acceleration on FPGA

Published:2020-08 Issue: Volume: Page:
ISSN:
Container-title:2020 30th International Conference on Field-Programmable Logic and Applications (FPL)
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Author:

Kulkarni Amit,Chiosa Monica,Preusser Thomas B.,Kara Kaan,Sidler David,Alonso Gustavo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9210705/9221504/09221525.pdf?arnumber=9221525

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A streaming algorithm and hardware accelerator to estimate the empirical entropy of network flows;Computer Networks;2023-12

2. In-Network Compression for Accelerating IoT Analytics at Scale;2023 IEEE Symposium on High-Performance Interconnects (HOTI);2023-08

3. Optimized algorithms and architectures for fast non-cryptographic hash functions in hardware;Microprocessors and Microsystems;2023-04

4. Optimistic Data Parallelism for FPGA-Accelerated Sketching;Proceedings of the VLDB Endowment;2023-01

5. High-Level Design Optimizations for Implementing Data Stream Sketch Frequency Estimators on FPGAs;Electronics;2022-07-31

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