Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs

Author:

Lin Jai-Ming,Huang Chung-Wei,Zane Liang-Chi,Tsai Min-Chia,Lin Che-Li,Tsai Chen-Fa

Funder

Ministry of Science and Technology of Taiwan

Publisher

IEEE

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Automated Physical Design Watermarking Leveraging Graph Neural Networks;Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD;2024-09-09

2. Design and Development of Serial Driver Verification and Test Module using Universal Verification Methodology;2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN);2024-05-03

3. Design and Development of Serial Driver Verification Scoreboard Module using UVM;2024 International Conference on Inventive Computation Technologies (ICICT);2024-04-24

4. Methodology for Timing Closure in VLSI Physical Design containing high clock to Q Memory Delay;2023 IEEE Silchar Subsection Conference (SILCON);2023-11-03

5. Routability-Driven Orientation-Aware Analytical Placement for System in Package;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

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