Design and Development of Serial Driver Verification Scoreboard Module using UVM
Author:
Affiliation:
1. Kalasalingam Academy of Research and Education,Department of Electronics and Communication,Madurai,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10543255/10544376/10544523.pdf?arnumber=10544523
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3. FPGA Based Efficient Interface Model for Scalefree Computer Network using I2C Bus Protocol;Venkateswaran;Advances in Computer Sci & Engg., National Polytechnic Institute, Mexico,2006
4. A timing-driven macro-cell placement algorithm
5. PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories
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