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A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs

  • Published:2007-12 Issue:6 Volume:54 Page:2065-2072
  • ISSN:0018-9499
  • Container-title:IEEE Transactions on Nuclear Science
  • language:
  • Short-container-title:IEEE Trans. Nucl. Sci.

Author:

Morgan Keith S.,McMurtrey Daniel L.,Pratt Brian H.,Wirthlin Michael J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Nuclear Energy and Engineering,Nuclear and High Energy Physics

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2. On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

3. Discussion of single event effect (SEE) influence and protection design strategy in avionics;2023 IEEE 18th Conference on Industrial Electronics and Applications (ICIEA);2023-08-18

4. Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction;International Journal of Electronics and Telecommunications;2023-07-26

5. The Path to Fault- and Intrusion-Resilient Manycore Systems on a Chip;2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S);2023-06
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