A twofold bio-inspired system for mitigating SEUs in the controllers of digital system deployed on FPGA
Author:
Funder
RIC, DRDO
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Information Systems,Theoretical Computer Science,Software
Link
https://link.springer.com/content/pdf/10.1007/s11227-023-05804-0.pdf
Reference28 articles.
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2. Bolchini C, Miele A, Santambrogio MD (2007) Tmr and partial dynamic reconfiguration to mitigate seu faults in fpgas. In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007). IEEE, pp 87–95
3. Kalganova T (2000) Bidirectional incremental evolution in extrinsic evolvable hardware. In: Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware. IEEE, pp 65–74
4. Shang Q, Chen L, Cui J, Lu Y (2020) Hardware evolution based on improved simulated annealing algorithm in cyclone v fpsocs. IEEE Access 8:64770–64782
5. Garnica O, Glette K, Torresen J (2018) Comparing three online evolvable hardware implementations of a classification system. Genet Program Evolvable Mach 19(1):211–234
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