Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Cited by
25 articles.
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1. Identification of Logic Paths Influenced by Severe Coupling Capacitances;Journal of Electronic Testing;2020-11-21
2. Introduction;Test Generation of Crosstalk Delay Faults in VLSI Circuits;2018-09-21
3. An output node split CMOS logic for high-performance and large capacitive-load driving scenarios;Microelectronics Journal;2018-02
4. Cross-Talk Delay Fault Test Generation;Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems;2014-07-17
5. Analytical Modeling of Single Event Transients Propagation in Combinational Logic Gates;IEEE Transactions on Nuclear Science;2012-08