An Improved Design of Low Power High Speed Configurable Logic Block using 90nm CMOS Technology
Author:
Affiliation:
1. Bangladesh University of Engineering and Technology,Department of Electrical and Electronic Engineering,Dhaka,Bangladesh
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10083318/10083503/10084130.pdf?arnumber=10084130
Reference15 articles.
1. Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry
2. Self-timed FPGA systems
3. Low-power CMOS digital design
4. Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL
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1. Design and Performance Analysis of Configurable Logic Block (CLB) for FPGA using Various Circuit Topologies;2024 3rd International Conference for Innovation in Technology (INOCON);2024-03-01
2. An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
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