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Gated clock routing for low-power microprocessor design

Published:2001-06 Issue:6 Volume:20 Page:715-722
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Jaewon Oh ,Pedram M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/20005/00924825.pdf?arnumber=924825

Cited by 41 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies;International Journal of Electronics;2022-12-28

3. Reliability-Aware 3-D Clock Distribution Network Using Memristor Ratioed Logic;IEEE Transactions on Components, Packaging and Manufacturing Technology;2019-09

4. A SAT-Based Methodology for Effective Clock Gating for Power Minimization;Journal of Circuits, Systems and Computers;2018-10-15

5. CHARSTAR;ACM SIGARCH Computer Architecture News;2017-09-14

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