Integration of Posit Arithmetic in RISC-V Targeting Low-Power Computations-Reference-Cited by-同舟云学术

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Integration of Posit Arithmetic in RISC-V Targeting Low-Power Computations

Published:2024-07-08 Issue: Volume:2019 Page:352-357
ISSN:
Container-title:2024 IEEE 24th International Conference on Nanotechnology (NANO)
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Author:

Mallasén David¹^ORCID,Murillo Raul²^ORCID,Del Barrio Alberto A.¹^ORCID,Botella Guillermo³^ORCID,Prieto-Matias Manuel¹^ORCID

Affiliation:

1. Universidad Complutense de Madrid,Facultad de Informática,Madrid,Spain,28040

2. Universidad Complutense de Madrid,Facultad de Ciencias Físicas,Madrid,Spain,28040

3. Instituto de Tecnologia del Conocimiento, Universidad Complutense de Madrid,Facultad de Informática,Madrid,Spain,28040

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10628446/10628545/10628939.pdf?arnumber=10628939

Reference31 articles.

1. IEEE Standard for Floating-Point Arithmetic,2019

2. What every computer scientist should know about floating-point arithmetic

3. Pracniques: further remarks on reducing truncation errors

4. The art of computer programming;Knuth,1997

5. Fast Reproducible Floating-Point Summation

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