On area-efficient low power array multipliers-Reference-Cited by-同舟云学术

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On area-efficient low power array multipliers

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Container-title:ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)
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Author:

Yuke Wang ,Yingtao Jiang ,Sha E.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7591/20701/00957483.pdf?arnumber=957483

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Low Power Parallel Multiplier;Journal of Low Power Electronics;2009-04-01

2. A new array architecture for signed multiplication using Gray encoded radix-2moperands;Integration;2007-02

3. Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks;Journal of Low Power Electronics;2005-12-01

4. A new architecture for signed radix-2/sup m/ pure array multipliers;Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

5. A new architecture for 2's complement Gray encoded array multiplier;Proceedings. 15th Symposium on Integrated Circuits and Systems Design

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