Implementation and verification practices of DVFS and power gating-Reference-Cited by-同舟云学术

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Implementation and verification practices of DVFS and power gating

Published:2009-04 Issue: Volume: Page:
ISSN:
Container-title:2009 International Symposium on VLSI Design, Automation and Test
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Author:

Shi-Hao Chen ,Jiing-Yuan Lin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5128899/5158074/05158084.pdf?arnumber=5158084

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10

2. A Survey on Power Gating Techniques in Low Power VLSI Design;Advances in Intelligent Systems and Computing;2016

3. A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer;IEEE Transactions on Circuits and Systems I: Regular Papers;2014-06

4. Verification work reduction methodology in low-power chip implementation;ACM Transactions on Design Automation of Electronic Systems;2013-01

5. Open SystemC Simulator with Support for Power Gating Design;International Journal of Reconfigurable Computing;2012

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