Single Event Upset Sensitivity of D-Flip Flop: Comparison of PDSOI With Bulk Si at 130 nm Technology Node-Reference-Cited by-同舟云学术

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Single Event Upset Sensitivity of D-Flip Flop: Comparison of PDSOI With Bulk Si at 130 nm Technology Node

Published:2017-01 Issue:1 Volume:64 Page:683-688
ISSN:0018-9499
Container-title:IEEE Transactions on Nuclear Science
language:
Short-container-title:IEEE Trans. Nucl. Sci.

Author:

Zhang Leqing,Xu Jialing,Fan Shuang,Dai Lihua,Bi Dawei,Lu Jian,Hu Zhiyuan,Zhang Mengying,Zhang Zhengxuan

Funder

Key Laboratory of Microsatellites, Chinese Academy of Sciences

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Nuclear Energy and Engineering,Nuclear and High Energy Physics

Link

http://xplorestaging.ieee.org/ielx7/23/7869242/07779103.pdf?arnumber=7779103

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multiple-Error Interceptive Voter Designs for Safety-Critical Applications;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18

2. An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14

3. Single Event Effect Mechanism Study in 130nm Fully Depleted SOI Technology Devices;IEICE Electronics Express;2024

4. Comparison of Total Ionizing Dose Effect on Tolerance of SCL 180 nm Bulk and SOI CMOS Using TCAD Simulation;Lecture Notes in Electrical Engineering;2022-12-04

5. Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods;International Journal of Innovative Technology and Exploring Engineering;2022-04-30

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