Reliability Performance of S-Connect Module (Bridge Technology) for Heterogeneous Integration Packaging

Author:

Jang Heejun1,Ahn Kyun1,Park Haesung1,Yong Gamhan1,Kim Jihyun1,Jeong YeonKi1,Sohn EunSook1,Hiner Dave2,Kelly Mike2,Hwang Taekyeong1,Do Wonchul1,Khim JinYoung1

Affiliation:

1. R&D, Amkor Technology Korea,Incheon,Korea

2. Advanced Package and Technology Integration, Amkor Technology,Inc.,Tempe,AZ,USA

Publisher

IEEE

Reference7 articles.

1. Wafer level system integration of the fifth generation CoWoS-S with high performance Si interposer at 2500mm2;huang;2021 IEEE 71st Electronic Components and Technology Conference (ECTC),0

2. Cost per yielded mm2 for a 250mm2 die;su;IEDM,2017

3. Chiplet meets the real world: benefits and limits of chiplet designs;naffziger;VLSI Symposia Joint Short Course,0

4. Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

5. Recent Advances and Trends in Advanced Packaging

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Signal integrity analysis of heterogeneous integration using Si bridge technology;2023 20th International SoC Design Conference (ISOCC);2023-10-25

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