Assembly Challenges and Approaches for 2.5D Chiplet Based System
Author:
Affiliation:
1. Institute of Microelectronics, Agency for Science, Technology and Research (A* STAR),Singapore,Singapore
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195700.pdf?arnumber=10195700
Reference8 articles.
1. Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB)
2. NetfFlex: A 22nm Multi-Chiplet Perception Accelerator in High Density Fan-Out Wafer-Level Packaging;chou;2022 IEEE Symposium on VLSI Technology and Circuits,0
3. Heterogeneous Integration for Chiplets on FOWLP Development Line
4. Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects Evaluation-Small Die Applications;gao;72nd ECTC San Diego,1981
5. Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions
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