Process Integration of Photonic Interposer for Chiplet-based 3D Systems
Author:
Affiliation:
1. CEA-Leti, Univ Grenoble Alpes,Grenoble,France
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195453.pdf?arnumber=10195453
Reference13 articles.
1. Integrated waveguide PIN photodiodes exploiting lateral Si/Ge/Si heterojunction
2. Estimation of Propagation Losses for Narrow Strip and Rib Waveguides
3. Multiple wavelength silicon photonic 200mm R&D platform for 25Gb/s and above applications;szelag;SPIE Photonics Europe 2016 - Proceedings of the SPIE,2016
4. Backside cavities for thermal tuning optimization of silicon ring resonators
5. 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters
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