A Hybrid Panel Level Package (Hybrid PLP) Technology Based on a 650-mm x 650-mm Platform-Reference-Cited by-同舟云学术

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A Hybrid Panel Level Package (Hybrid PLP) Technology Based on a 650-mm x 650-mm Platform

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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Author:

O'Toole Eoin¹,Silva Jose Luis¹,Cardoso Filipe¹,Silva Jose¹,Alves Luis¹,Souto Marcio¹,Delduque Nuno¹,Coelho Anibal¹,Silva Jose Miguel¹,Do WonChul²,Khim JinYoung²

Affiliation:

1. Amkor Technology,Portugal

2. Amkor Technology,Incheon,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816484.pdf?arnumber=9816484

Reference4 articles.

1. FOWLP technology as wafer level system in packaging (SiP) solution;wakabayashi;2017 International Conference on Electronics Packaging (ICEP2017),2017

2. System in wafer-level package technology with RDL-first process

3. Embedded wafer level ball grid array (eWLB)

4. Wafer level chip scale packaging (WL-CSP): an overview

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multiple System and Heterogeneous Integration with TSV-Less Interposers;Chiplet Design and Heterogeneous Integration Packaging;2023

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