Fan-out Wafer Level Package for Memory Applications-Reference-Cited by-同舟云学术

Fan-out Wafer Level Package for Memory Applications

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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Author:

Son Ho-Young¹,Sung Ki-Jun¹,Choi Bok-Kyu¹,Kim Jong-Hoon¹,Lee Kangwook¹

Affiliation:

1. SK Hynix Inc.,Icheon-si,Republic of Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816532.pdf?arnumber=9816532

Reference5 articles.

1. Reliability of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Re-Distributed Layers

2. InFO (Wafer Level Integrated Fan-Out) Technology

3. Evaluation of chip stackable FOWLP technology for high performance and large memory capacity;kim;Proceedings in Korean Microelectronics and Packaging Society,2020

4. Interconnect Challenges in Memory Packaging;son;19th International Symposium on Microelectronics and Packaging,2021

5. Reliability studies on micro-bumps for 3-D TSV integration

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