A Robust CTS algorithm using the H-Tree to minimize local skews of higher frequency targets of the SOC designs
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9194988/9201947/09202022.pdf?arnumber=9202022
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs;Electronics;2023-10-19
2. Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths and Optimizing Clock Tree in RTL Design Time;2023 14th International Conference on Information and Communication Technology Convergence (ICTC);2023-10-11
3. Application Specific Digital and Mixed-Signal Integrated Circuit Designs Based on Algorithm Hardware Co-Design;2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT);2022-02-16
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