Multiple transient faults in logic: an issue for next generation ICs?-Reference-Cited by-同舟云学术

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Multiple transient faults in logic: an issue for next generation ICs?

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Container-title:20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
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Author:

Rossi D.,Omana M.,Toma F.,Metra C.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/10366/32969/01544534.pdf?arnumber=1544534

Cited by 42 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

3. A guided debugger-based fault injection methodology for assessing functional test programs;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

4. Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection;2022 IEEE 23rd Latin American Test Symposium (LATS);2022-09-05

5. A Soft Error Detection and Recovery Flip-Flop for Aggressive Designs With High-Performance;IEEE Transactions on Device and Materials Reliability;2022-06

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