Closed-Form Expressions of Parasitic Parameters for Different Sidewall Roughness of Through-Silicon Vias Interconnects-Reference-Cited by-同舟云学术

Closed-Form Expressions of Parasitic Parameters for Different Sidewall Roughness of Through-Silicon Vias Interconnects

Published:2024-02 Issue:2 Volume:71 Page:1160-1165
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Fang Zhen¹^ORCID,Zhang Jihua¹^ORCID,Gao Libin¹,Li Shuqi¹,Liu Jinxu¹,Chen Hongwei¹^ORCID,Yang Xiaolin²^ORCID,Li Wenlei¹^ORCID,Cai Xingzhou³

Affiliation:

1. School of Integrated Circuit Science and Engineering, State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China

2. School of Physics, University of Electronic Science and Technology of China, Chengdu, China

3. Chengdu Micro-Technology Company, Ltd., Chengdu, China

Funder

Fundamental Research Funds for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10413236/10364729.pdf?arnumber=10364729

Reference24 articles.

1. Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

2. Closed-Form Expressions for the Resistance and the Inductance of Different Profiles of Through-Silicon Vias

3. An Analytical Through Silicon Via (TSV) Surface Roughness Model Applied to a Millimeter Wave 3-D IC

4. Investigating the role of sidewall surface roughness on the performance of through silicon vias

5. Electrical modeling and analysis of sidewall roughness of through silicon vias in 3D integration