Nanosized-Metal-Grain-Pattern-Dependent Threshold-Voltage Models for the Vertically Stacked Multichannel Gate-All-Around Si Nanosheet MOSFETs and Their Applications in Circuit Simulation-Reference-Cited by-同舟云学术

Nanosized-Metal-Grain-Pattern-Dependent Threshold-Voltage Models for the Vertically Stacked Multichannel Gate-All-Around Si Nanosheet MOSFETs and Their Applications in Circuit Simulation

Published:2024-01 Issue:1 Volume:71 Page:350-358
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Sung Wen-Li¹,Li Yiming¹^ORCID,Chuang Min-Hui¹

Affiliation:

1. Department of Electronics and Electrical Engineering, Parallel and Scientific Computing Laboratory, Institute of Communications Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

Funder

National Science and Technology Council (NSTC), Taiwan

“2022 Qualcomm Taiwan Research Program, National Yang Ming Chiao Tung University (NYCU),”

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10382412/10310111.pdf?arnumber=10310111

Reference43 articles.

1. Celebrating 75 years of the transistor A look at the evolution of Moore’s Law innovation

2. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

3. A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

4. Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I–Modeling and Simulation Method

5. Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

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