Noise Margin analysis of Efficient CNTFET- based Standard Ternary Inverter
Author:
Affiliation:
1. Manipal University Jaipur,Department of ECE,Jaipur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10079844/10079947/10080321.pdf?arnumber=10080321
Reference19 articles.
1. Design of Universal Logic Gates based on;tapiawala,2014
2. A novel CNTFET-based ternary logic gate design
3. CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic
4. Design of CMOS ternary logic family based on single supply voltage
5. Carbon nanotube feedback-gate field-effect transistor: Suppressing current leakage and increasing on/off ratio;qiu;ACS Nano,2015
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2. Logical Review of CNTFET-based Ternary Universal Gates;2023 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech);2023-12-18
3. Design Evaluation and Performance Prediction of Different SRAM Cell Topologies through Inverter Optimization for the 5nm Technology Node using GAA CNTFETs;2023 IEEE Silchar Subsection Conference (SILCON);2023-11-03
4. Performance Analysis of Standard Quaternary Inverters for Noise Margin;2023 International Conference on Ambient Intelligence, Knowledge Informatics and Industrial Electronics (AIKIIE);2023-11-02
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