APR-16: The Physical Design of a Reconfigurable Array Processor Chip-Reference-Cited by-同舟云学术

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APR-16: The Physical Design of a Reconfigurable Array Processor Chip

Published:2022-10-28 Issue: Volume: Page:
ISSN:
Container-title:2022 7th International Conference on Integrated Circuits and Microsystems (ICICM)
language:
Short-container-title:

Author:

Xiao Yangfan¹,Shan Rui¹,Ye Zekun¹,Jiang Lin²,Liao Wang¹,Zhang Baoxiang³

Affiliation:

1. Xi’an University of Posts and Telecommunications,School of Electronic Engineering,Xi’an,China

2. Xi’an University of science and technology,School of Computer Science and Technology,Xi’an,China

3. Xi’an University of Posts and Telecommunications,Xi’an,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011353.pdf?arnumber=10011353

Reference17 articles.

1. Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping

2. DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures

3. HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications

4. Design and implementation of reconfigurable video array processor test platform;lin;Journal of System Simulation,2020

5. Design of a controllable delay asynchronous fifo circuit;tingting;Microelectronics,2022

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