Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping
Author:
Affiliation:
1. Keio University, Hiyoshi, Yokohama, Japan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3241793.3241806
Reference18 articles.
1. Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips
2. EPIMap
3. Energy-aware loops mapping on multi-vdd CGRAs without performance degradation
4. Body bias optimization for variable pipelined CGRA
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