A 9-bit 500-MS/s 2-then-1b/cycle SAR ADC with Dynamic Background Offset Calibration Technique
Author:
Affiliation:
1. Guilin University of Electronic Technology,Guangxi Key Laboratory of Precision Navigation Technology and Application,Guilin,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011243.pdf?arnumber=10011243
Reference12 articles.
1. A 0.024 mm² 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in 65nm CMOS;wei;IEEE International Solid State Circuits Conference,2011
2. A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC
3. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
4. A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS
5. A Low Power 8-bit 2b/Cycle SAR ADC with Multiple Calibration Techniques
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