High Performance Injection-Locked PLL Architectures: An Overview
Author:
Affiliation:
1. Fudan University,State Key Laboratory of ASIC and System,Shanghai,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011234.pdf?arnumber=10011234
Reference10 articles.
1. A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop
2. A multiple-crystal interface PLL with VCO realignment to reduce phase noise
3. A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response
4. An injection-locked ring PLL with self-aligned injection window
5. A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth
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1. An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS;Journal of Low Power Electronics and Applications;2023-12-17
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