Author:
Tombs Frederick,Mellat Alireza,Kapre Nachiket
Cited by
3 articles.
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1. Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01
2. SPADES: A Productive Design Flow for Versal Programmable Logic;2023 33rd International Conference on Field-Programmable Logic and Applications (FPL);2023-09-04
3. OverGen: Improving FPGA Usability through Domain-specific Overlay Generation;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10