A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality-Reference-Cited by-同舟云学术

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A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality

Published:2016-11 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE 25th Asian Test Symposium (ATS)
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Author:

Gharehbaghi Amir Masoud,Fujita Masahiro

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7795842/7796050/07796077.pdf?arnumber=7796077

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SFLL-AD: A Self-adaptive and Secure Logic Locking;IEICE ELECTRON EXPR;2023

2. SFLL-AD: A Self-adaptive and Secure Logic Locking;IEICE Electronics Express;2023

3. Signal Selection Methods for Debugging Gate-Level Sequential Circuits;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2019-12-01

4. Formal Verification and Debugging of VLSI Logic Design for Systems Dependability: Experiments and Evaluation;VLSI Design and Test for Systems Dependability;2018-07-21

5. Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers;2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2018-07

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