Signal Selection Methods for Debugging Gate-Level Sequential Circuits-Reference-Cited by-同舟云学术

Signal Selection Methods for Debugging Gate-Level Sequential Circuits

Published:2019-12-01 Issue:12 Volume:E102.A Page:1770-1780
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KIMURA Yusuke¹,GHAREHBAGHI Amir Masoud²,FUJITA Masahiro²

Affiliation:

1. Department of Electrical Engineering and Information Systems, The University of Tokyo

2. System Design Research Center (previously VLSI Design and Education Center), The University of Tokyo

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E102.A/12/E102.A_1770/_pdf

Reference19 articles.

1. [1] Y. Kimura, A.M. Gharehbaghi, and M. Fujita, “Signal selection methods for efficient multi-target correction,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, May 2019. 10.1109/iscas.2019.8702149

2. [2] M. Fujita, T. Kakuda, and Y. Matsunaga, “Redesign and automatic error correction of combinational circuits,” Logic and Architecture Synthesis, pp.253-262, 1991.

3. [3] D. Brand, A. Drumm, S. Kundu, and P. Narain, “Incremental synthesis,” Proc. 1994 IEEE/ACM International Conference on Computer-aided Design, ICCAD'94, pp.14-18, IEEE Computer Society Press, Los Alamitos, CA, USA, 1994. 10.1109/iccad.1994.629736

4. [4] A.Q. Dao, N.Z. Lee, L.C. Chen, M.P.H. Lin, J.H.R. Jiang, A. Mishchenko, and R. Brayton, “Efficient computation of ECO patch functions,” Proc. 55th Annual Design Automation Conference, DAC'18, pp.51:1-51:6, ACM, New York, NY, USA, 2018. 10.1109/dac.2018.8465898

5. [5] A.M. Gharehbaghi and M. Fujita, “A new approach for debugging logic circuits without explicitly debugging their functionality,” 2016 IEEE 25th Asian Test Symposium (ATS), pp.31-36, Nov. 2016. 10.1109/ats.2016.54

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