Author:
Seung Pyo Jung ,Jingzhe Xu ,Donghoon Lee ,Ju Sung Park ,Kang-joo Kim ,Koon-shik Cho
Cited by
2 articles.
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1. Design of 32-bit RISC V using area efficient multiplier based on homogeneous hybrid adder;INTELLIGENT BIOTECHNOLOGIES OF NATURAL AND SYNTHETIC BIOLOGICALLY ACTIVE SUBSTANCES: XIV Narochanskie Readings;2023
2. Design and Verification of 16 bit RISC Processor Using Vedic Mathematics;2021 International Conference on Emerging Smart Computing and Informatics (ESCI);2021-03-05