An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$m CMOS-Reference-Cited by-同舟云学术

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An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$m CMOS

Published:2010-02 Issue:2 Volume:45 Page:391-400
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Peach Charles T.,Moon Un-Ku,Allstot David J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/5405130/05405158.pdf?arnumber=5405158

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2.24-mW, 61.8-dB SNDR, 20-MS/s Pipelined ADC With Charge-Pump-Based Dynamic Biasing for Power Reduction in Op Amp Sharing;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-06

2. Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs;Journal of Signal Processing Systems;2012-06-07

3. An 8-bit 19 MS/s low-power 0.35 μm CMOS pipelined ADC for DVB-H;Integration;2012-03

4. Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp;IEEE Journal of Solid-State Circuits;2010-12

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