Author:
Gupta Subhanshu,Tang Yi,Paramesh Jeyanandh,Allstot David J.
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
Reference15 articles.
1. Peach, C. T., Moon, U.-K., & Allstot, D. J. (2010). An 11.1 mW 42 MS/s 10b ADC with two-step settling in 0.18 μm CMOS. IEEE Journal of Solid-State Circuits, 45, 391–400.
2. Rutten, R., Breems, L. J., & Wetzker, G. (2006). Digital calibration of a continuous-time cascaded ΣΔ modulator based on variance derivative estimation. IEEE Processing European Solid-State Circuits Conference, pp. 199–202.
3. Shu, Y.-S., Kamiishi, J., Tomioka, K., Hamashita, K., & Song, B.-S. (2010). LMS-Based noise leakage calibration of cascaded continuous-time modulators. IEEE Journal of Solid-State Circuits, 45, 368–379.
4. Bosi, A., Panigada, A., Cesura, G., & Castello, R. (2005). An 80 MHz 4X oversampled cascaded ΣΔ-pipeline ADC with 75 dB DR and 87 dB SFDR. IEEE International Solid- State Circuits Conference, pp. 174–175.
5. Murmann, B. (2006). Digitally assisted analog circuits. IEEE Micro, 26, 38–47.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献