A novel high-speed sense amplifier for Bi-NOR flash memories

Author:

Chiu-Chiao Chung ,Hongchin Lin ,Yen-Tai Lin

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A low-power high-performance voltage sense amplifier for static RAM and comparison with existing current/voltage sense amplifiers;International Journal of Information Technology;2022-04-12

2. Parametric Extraction and Comparison of Different Voltage-Mode based Sense Amplifier Topologies;2021 3rd International Conference on Advances in Computing, Communication Control and Networking (ICAC3N);2021-12-17

3. Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme;IEICE Transactions on Electronics;2020-08-01

4. Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array;2020 24th International Symposium on VLSI Design and Test (VDAT);2020-07

5. 28nm STT-MRAM Array and Sense Amplifier;2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST);2019-05

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