Author:
Shah S.,Al-Khalili A.J.,Al-Khalili D.
Cited by
13 articles.
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1. An energy efficient multipliers using reversible gates;Journal of Physics: Conference Series;2020-12-01
2. An Implementation of Area Optimized Low Power MAC;JOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES;2019-06-26
3. Efficient Set-Bit Driven Shift-Add Binary Multiplier;Advances in Intelligent Systems and Computing;2018-11-02
4. Design of Low Power Digital Multiplier Using Dual Threshold Voltage Adder Module;Procedia Engineering;2012
5. On Built-In Self-Test for multipliers;Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon);2010-03