Author:
Weinberger A.,Smith J. L.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Cited by
12 articles.
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2. Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic;2022 IEEE 52nd International Symposium on Multiple-Valued Logic (ISMVL);2022-05
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4. On high-performance parallel decimal fixed-point multiplier designs;Computers & Electrical Engineering;2014-10
5. An Algebra of Scans;Lecture Notes in Computer Science;2004