On high-performance parallel decimal fixed-point multiplier designs

Author:

Zhu Ming,Jiang Yingtao,Yang Mei,Chen Tianding

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference25 articles.

1. Readings in computer architecture;Hill,2000

2. Cowlishaw MF. Decimal floating-point: algorithm for computers. In: Proceedings of 16th symposium of computer architecture, June 2003.pp. 104–11.

3. IEEE Computer Society. IEEE standard for floating point arithmetic, August 2008.

4. Lang Tomas, Nannarelli Alberto. A radix-10 combinational multiplier. In: Fortieth asilomar conference on signals, systems, and computers, ACSSC ‘06, October 29–November 1, 2006. p. 313–7.

5. Vazquez A, Antelo E, Montuschi P. A new family of high-performance parallel decimal multipliers. In: 18th IEEE symposium on computer arithmetic. Montpellier, France, June 2007. p. 195–204.

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