Design of High Speed, Low Power 16x16 Vedic Multiplier With Adiabatic Logic

Author:

Arunkumar K.1,Mangayarkarasi P.1,Jackson Beulah1,Juliette A. Anitha2

Affiliation:

1. Saveetha Engineering College,Department of ECE,Chennai

2. Loyola ICAM College of Engineering and Technology,Department of ECE,Chennai

Publisher

IEEE

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Area and Speed-Efficient Floating-Point Arithmetic Logical Unit Implementation on FPGA;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06

2. Area And Speed-Efficient Vedic RISC Processors for Embedded Systems;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06

3. State of the art design of adder modules: performance validation of GDI methodology for energy harvesting applications;International Journal of System Assurance Engineering and Management;2023-07-26

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