Multi-step and high-resolution vernier-based TDC architecture
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8255703/8268805/08268819.pdf?arnumber=8268819
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Novel Cascaded Ring Oscillator Vernier based TDC Architecture with a Feedthrough Reference Oscillator;2023 IEEE Nuclear Science Symposium, Medical Imaging Conference and International Symposium on Room-Temperature Semiconductor Detectors (NSS MIC RTSD);2023-11-04
2. A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC;Sensors;2021-12-31
3. An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept;Proceedings of the 26th Asia and South Pacific Design Automation Conference;2021-01-18
4. Analog and Digital Signal Processing for Nuclear Instrumentation;Topics in Applied Physics;2021
5. A 6-bit hierarchal TDC architecture for time-based ADCs;Analog Integrated Circuits and Signal Processing;2020-10-17
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