Author:
DeOrio Andrew,Wagner Ilya,Bertacco Valeria
Cited by
16 articles.
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1. EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory Verification;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-02
2. ReDeSIGN: Reuse of Debug Structures for Improvement in Performance Gain of NoC based MPSoCs;IEEE Transactions on Emerging Topics in Computing;2022
3. A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors;2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID);2020-01
4. Reusing Trace Buffers as Victim Caches;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-09
5. A Survey on Post-Silicon Functional Validation for Multicore Architectures;ACM Computing Surveys;2018-07-31