A Domain-Specific On-Chip Network Design for Large Scale Cache Systems

Author:

Jin Yuho,Kim Eun Jung,Yum Ki Hwan

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Adaptive memory-side last-level GPU caching;Proceedings of the 46th International Symposium on Computer Architecture;2019-06-22

2. Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems;Future Generation Computer Systems;2018-01

3. Carpool;Proceedings of the International Conference on Supercomputing - ICS '17;2017

4. Multi-Core Cache Hierarchies;Synthesis Lectures on Computer Architecture;2011-05-22

5. An analysis of on-chip interconnection networks for large-scale chip multiprocessors;ACM Transactions on Architecture and Code Optimization;2010-04

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