A 47 GHz to 70 GHz Frequency Doubler Exploiting 2nd-Harmonic Feedback with 10.1 dBm Psat and ntotal of 22% in 65 nm CMOS
Author:
Affiliation:
1. Oregon State University,High-Speed Integrated Circuits Lab,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10186107/10186112/10186145.pdf?arnumber=10186145
Reference9 articles.
1. A Broadband mm-Wave and Terahertz Traveling-Wave Frequency Multiplier on CMOS
2. A High Efficiency E-Band CMOS Frequency Doubler With a Compensated Transformer-Based Balun for Matching Enhancement
3. A 7.2-mW V-Band Frequency Doubler With 14% Total Efficiency;sutbas;IEEE MWCL,2022
4. A 60 GHz CMOS-SOI Stacked Push-Push Frequency Doubler with 12 dBm Output Power and 20% Efficiency
5. A 19.5% Efficiency 51–73-GHz High-Output Power Frequency Doubler in 65-nm CMOS
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1. A 43–84 GHz, Wideband Frequency Doubler with a Symmetric, AC-Terminated Transformer Balun;2024 IEEE/MTT-S International Microwave Symposium - IMS 2024;2024-06-16
2. A Frequency Doubler With Second Harmonic Feedback for Wideband, Efficient Frequency Multiplication at Millimeter-Wave;IEEE Transactions on Microwave Theory and Techniques;2024-05
3. Digital Predistortion of Frequency Multiplier-Based Vector Signal Sources With Constrained Transmitter and Observation Receiver Bandwidth;IEEE Transactions on Microwave Theory and Techniques;2024
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