A 60 GHz CMOS-SOI Stacked Push-Push Frequency Doubler with 12 dBm Output Power and 20% Efficiency-Reference-Cited by-同舟云学术

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A 60 GHz CMOS-SOI Stacked Push-Push Frequency Doubler with 12 dBm Output Power and 20% Efficiency

Published:2021-06-07 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE MTT-S International Microwave Symposium (IMS)
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Author:

Eladwy Mahitab,Xia Jingjing,Ayed Ahmed Ben,Boumaiza Slim

Funder

Natural Sciences and Engineering Research Council of Canada (NSERC)

United States Army Research Laboratory

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9574790/9574791/09574811.pdf?arnumber=9574811

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 60 GHz low phase noise VCO with second harmonic tail extraction in 40-nm CMOS;AEU - International Journal of Electronics and Communications;2024-11

2. A 43–84 GHz, Wideband Frequency Doubler with a Symmetric, AC-Terminated Transformer Balun;2024 IEEE/MTT-S International Microwave Symposium - IMS 2024;2024-06-16

3. A Frequency Doubler With Second Harmonic Feedback for Wideband, Efficient Frequency Multiplication at Millimeter-Wave;IEEE Transactions on Microwave Theory and Techniques;2024-05

4. Digital Predistortion of Frequency Multiplier-Based Vector Signal Sources With Constrained Transmitter and Observation Receiver Bandwidth;IEEE Transactions on Microwave Theory and Techniques;2024

5. A V-Band 16% Efficiency Frequency Doubler-Based RF Beamforming Front-End Module for Vector Modulated Signal Transmission;2023 53rd European Microwave Conference (EuMC);2023-09-19

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