A 0.2-2 GHz Time-Interleaved Multi-Stage Switched-Capacitor Delay Element Achieving 448.6 ns Delay and 330 ns/mm2 Area Efficiency
Author:
Affiliation:
1. Sandia National Laboratories,USA
Funder
Sandia National Laboratories
U.S. Department of Energy's
National Nuclear Security Administration
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9862947/9862948/09863079.pdf?arnumber=9863079
Reference8 articles.
1. A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay–Bandwidth Limit
2. A 4-Element 800MHz-BW 29mW True-Time-Delay Spatial Signal Processor Enabling Fast Beam-Training with Data Communications
3. In-Band Full-Duplex Operation in High-Speed Mobile Environments: Not So Fast!
4. Gigahertz Low-Loss and High Power Handling Acoustic Delay Lines Using Thin-Film Lithium-Niobate-on-Sapphire
5. A 0.46-mm$ ^{2}$ 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS
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1. Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element;Integration;2024-05
2. A 28 nm CMOS Dual-Band Concurrent WLAN and Narrow Band Transmitter With On-Chip Feedforward TX-to-TX Interference Cancellation Path for Low Antenna-to-Antenna Isolation in IoT Devices;IEEE Journal of Solid-State Circuits;2024-05
3. A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm2 Area Efficiency;IEEE Journal of Solid-State Circuits;2023-08
4. A 28nm CMOS Dual-Band Concurrent WLAN and Narrow Band Transmitter with On-chip Feedforward TX-to-TX Interference Cancellation Path for Low Antenna-to-Antenna Isolation in IoT Devices;2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2023-06-11
5. Two-Dimensional Phased-Array Receiver Based on Integrated Silicon True Time Delay Lines;IEEE Transactions on Microwave Theory and Techniques;2023-03
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