A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm<sup>2</sup> Area Efficiency-Reference-Cited by-同舟云学术

A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm² Area Efficiency

Published:2023-08 Issue:8 Volume:58 Page:2349-2359
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Forbes Travis¹^ORCID,Magstadt Benjamin¹^ORCID,Moody Jesse¹,Saugen Justine¹,Suchanek Andrew¹,Nelson Spencer¹

Affiliation:

1. Sandia National Laboratories, Albuquerque, NM, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/4/10192489/10089498-aam.pdf

Reference20 articles.

1. Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

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3. Jitter requirements of the sampling clock in software radio receivers

4. Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming

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