Nanoscale Thermal Transport in Vertical Gate- All-Around Junctionless Nanowire Transistors— Part II: Multiphysics Simulation
Author:
Affiliation:
1. IMS Laboratory, University of Bordeaux, Bordeaux, France
2. LAAS CNRS, UPR 8001, CNRS, Université of Toulouse, Toulouse, France
Funder
Project FVLLMONTI
European Union’s Horizon 2020 Research and Innovation Program
Laboratoire d’analyse et d’architecture des systèmes (LAAS)-Centre national de la recherche scientifique (CNRS) Micro and Nanotechnologies Platform, a member of the Renatech French National Network
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10328902/10281392.pdf?arnumber=10281392
Reference36 articles.
1. Ballistic Phonon Transport in Holey Silicon
2. Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs
3. Phonon hydrodynamics for nanoscale heat transport at ordinary temperatures
4. Thermal consideration in nanoscale gate-all-around vertical transistors
5. Ballistic thermal transport in silicon nanowires
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2. Microscopic origin of heat vorticity in quasi-ballistic phonon transport;International Journal of Heat and Mass Transfer;2024-07
3. Localized Phonon Transport Study of GaN/SiO2 Core/shell Nanowires under Thermal-Stress Coupling;Langmuir;2024-05-04
4. Analysis of GAAFET’s transient heat transport process based on phonon hydrodynamic equations;Acta Physica Sinica;2024
5. Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods;IEEE Transactions on Electron Devices;2023-12
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