A Cascode Current Mirror Based 90 mV to 1.8 V Level Shifter with Alleviated Delay

Author:

Jaisinghani Divisha1,B Shree Deeksha1,U S Aarthi1,Pande Kirti S.1

Affiliation:

1. Amrita School of Engineering, Amrita Vishwa Vidyapeetham,Bangalore,India

Publisher

IEEE

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Current Mirror based Level Shifter aiding multitudinous conversion ranges;2024 International Conference on Integrated Circuits and Communication Systems (ICICACS);2024-02-23

2. Backend Quality Analysis For I/O Pad;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02

3. Robust Body Biased Level Shifter;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13

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