Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping

Author:

Cong J.,Yean-Yow Hwang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fast Exact NPN Classification with Influence-Aided Canonical Form;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

2. Technology Mapping of Logic Functions in Complex Logic Blocks;Lecture Notes in Electrical Engineering;2020-11-08

3. Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm;IEEE Transactions on Computers;2020-09-01

4. An efficient NPN Boolean matching algorithm based on structural signature and Shannon expansion;Cluster Computing;2018-01-31

5. Computing Affine Equivalence Classes of Boolean Functions by Group Isomorphism;IEEE Transactions on Computers;2016-12-01

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